PCIe 4.0主板现在才开始向客户发货，但这并没有减缓这一关键外围连接标准的发展。PCIe 6.0已经摆在桌面上，与当前的尖端标准相比有了具体的改进。
由于PCIe正在成为各种形状和尺寸的计算机的基础，因此值得讨论一下PCIe是什么、它的用途以及新的PCIe 6.0将在未来提供什么。
PCIe 基础知识
PCIe 是Peripheral Component Interconnect Express的缩写。一些接触过计算机一段时间的读者可能还记得旧的PCI标准，但PCIe是原始PCI标准，就像战斗机是纸飞机一样。
PCIe既是一种协议，又是一种物理硬件连接标准。最常见的PCIe硬件连接标准是主板扩展槽。您将扩展卡连接到这些插槽，然后通过连接引脚进行通信。但是，可以通过其他类型的连接发送PCIe协议信号。
使用M.2(M.2)连接器的 NVME SSD可以使用PCIe，这与通过标准PCIe插槽连接的SSD的计算机似乎没有什么不同。(SSD)Thunderbolt 3和 4 标准还支持通过电缆发送PCIe信号。(PCIe)这就是eGPU(eGPUs)（外部显卡）的可能方式。
PCIe设备以串行方式发送数据，但跨越多个并行通道。计算机主板上的 x16 PCIe插槽可同时容纳 16 个数据通道。PCIe还提供 x8、x4 和 x1 插槽。通常，显卡使用 x16 插槽是因为它们需要尽可能多的带宽。虽然较慢的插槽通常在物理上更短，但除了主要插槽之外，x16 长度通常是 x8。
PCIe卡提供向后兼容性和交叉兼容性，因此您可以将 x4 卡插入任何物理上可以容纳它的PCIe插槽。(PCIe)只是你会浪费x4 卡不使用的任何PCIe通道。(PCIe)在例如 4.0 插槽中使用PCIe 5.0卡也是如此。(PCIe 5.0)它会起作用，但仅限于最低公分母。
谁决定 PCIe 标准？
PCI Express标准由PCI Special Interest Group ( PCI-SIG ) 设计和批准，该组织由电子和计算机行业的成员组成，对该技术有既得利益。
PCI-SIG成立于 1992 年，是一个致力于帮助计算机制造商正确实施Intel PCI标准的组织。今天，它是一个拥有 800 多名成员的非营利组织。
PCI-SIG板有AMD、ARM、Dell、IBM、Intel、Nvidia、Qualcomm等成员。您可能会将这些名称视为主要的计算设备制造商，并且拥有共享标准会使他们的工作更加轻松，更不用说他们客户的生活了！
PCIe 有什么用途？
我们已经在上面提到了扩展卡和SSD(SSDs)，因此您可能对 PCIe 的用途有了大致的了解。
PCIe标准几乎可以连接您能想象到的任何外部外围设备。它提供比USB更宽的带宽，尤其是在查看多个通道时。PCIe还提供了到CPU的直接路径，使其非常适合高速、低延迟的应用程序。
现代 GPU(Modern GPUs)使用 16 条 PCIe带宽通道来最大限度地提高其性能，但并非每个外围设备都需要那么多带宽。最新的PCIe 4.0 固态硬盘(SSDs)“仅”使用四个通道，但这足以让SATA标准彻底崩溃。虽然SATA最高可达 600 MB/s，但高端PCIe 4.0驱动器的移动速度可以超过 7000 MB/s。
PCIe扩展卡还可以容纳声卡(sound cards)、视频采集卡、10Gb以太网(Ethernet)适配器、WiFi 6卡、 Thunderbolt或USB控制器等。集成到计算机主板的外围设备也使用PCI Express。只是接线是永久性的，而不是插槽的形式。
PCIe 6.0(Does PCIe 6.0) 对PCIe 5.0有何改进(Improve)？
标题的改进通常是每次PCIe修订后数据速率的一大飞跃。这就是每秒可以通过总线传输的信息量。
在那个部门，PCIe 6.0并没有让人失望。它将PCIe 5.0(PCIe 5.0)的巨大数据传输速率从每秒 32 Gigatransfers ( GT/s ) 提高到每通道64 GT/sPCIe 5.0(Whereas PCIe 5.0)可以移动 63 GB(Gigabytes) /秒 ( GB/s )，而 6.0 可以移动到 128 GB/s。这是通过 x16 连接，更多的次要连接缩小。这意味着 x8 PCIe 6.0插槽现在具有与 x16 5.0 插槽一样高的性能。
这为未来的GPU(GPUs)和超快速存储解决方案创造了充足的空间。更不用说通过PCIe或提供Thunderbolt和USB 4的扩展卡连接的外部设备的惊人范围。
PCI Express 6.0 的新功能
在一代人的时间里实现如此巨大的性能飞跃并非易事。为了达到这些数字，PCI-SIG工程师必须开发一些创新的新方法来移动电子。
PAM4 信令(PAM4 Signaling)
很(Quite)可能，与前几代接口相比 ， PCIe 6.0最显着的变化是数据的编码方式。
PCI Express 6.0使用PAM4，它是 Pulse Amplitude Modulation 的缩写，具有四个级别。( Pulse Amplitude Modulation with four levels.)如果您对电波形有所了解，您就会知道波的“幅度”是波峰与基线的距离。
较旧的NRZ（不归零(Non-return-to-zero)）PCIe编码在一个时钟周期内每个脉冲只有两个幅度电平。PCIe 6 将其翻倍至四，增加了每个周期编码的数据量。
前向纠错 (FEC)(Forward Error Correction (FEC))
虽然PAM4编码方法显着提高了速度，但它也大大提高了误码率。换句话说，一个到达它的目的地而不是一个零，反之亦然。
为了解决这个问题，PCIe 6.0具有一个新的前向纠错功能，该功能借助强大的(Forward Error Correction)CRC（循环冗余校验(Cyclic Redundancy Check)）实现来检查以确保数据到达应去的地方而不会损坏。
在管道中添加更多纠错步骤的一个危险是您会增加更多延迟。对于各种高速计算机组件，额外的延迟越来越受到关注。(Additional)尽管他们可以转移越来越多的数据，但他们需要更长的时间来响应数据请求，这可能会导致其自身的问题。
(FEC)与以前版本的PCIe相比， (PCIe)FEC旨在增加不超过 2 纳秒的延迟，这是人类无法检测到的一点点额外延迟。
FLIT 模式(FLIT Mode)
FLIT模式是为改进(FLIT)PCIe 6.0中的纠错而引入的另一项措施。它使用专用的板载流量控制单元将数据组织成统一大小的单元。这是检查数据包错误所必需的，因为您可以将算法应用于每个数据包并检查数据包在到达管道的另一端时是否仍然给出结果。
事实证明，FLIT模式在其他地方也带来了显着的效率提升。它有助于降低延迟，提高带宽使用效率，并让PCIe 6.0消除以前版本的大部分编码开销。因此，尽管PAM4增加了高达 2ns 的延迟，但FLIT模式在其他方面节省了延迟。
L0p 模式(L0p Mode)
PCIe 6.0中一个有趣的特性是L0p模式。此模式减少了外设用于发送和接收数据的通道数。因此，如果您的笔记本电脑使用电池供电，而GPU不需要 16 通道来完成当前的工作，它将下降到只使用所需的通道数量，通过提高电源效率来节省电力。
您应该等待 PCIe 6.0 吗？
如果您正在考虑尽快购买或建造一台新计算机，您是否应该等待PCIe 6.0主板首先问世？尝试构建面向未来的计算机总是很诱人。如果出现需要PCIe 6.0才能充分发挥其潜力的新GPU或SSD怎么办？(SSD)
这个问题的简短回答是您不必担心等待PCIe 6.0。在撰写本文时，PCIe 5.0主板才刚刚开始向消费者推出，即使是当前最高端的GPU(GPUs)也远不需要PCIe 5.0。
在比较在(benchmarks)PCIe 3.0和 4.0 上运行的(PCIe 3.0)RTX 3080或 RTX 3090等旗舰卡的基准测试中，性能差异介于零和 3% 之间。是的，这是正确的。我们现在才达到PCIe 3.0的极限，而这仅适用于地球上最昂贵的GPU 。(GPUs)不要出汗——至少几年内不会。
请记住(Remember)，PCI-SIG仅在纸上发布了 6.0 版的最终PCIe规范。(PCIe)虽然最终规范不会改变，但我们还需要一段时间才能看到很多支持它的硬件，至少在消费领域是这样。
PCIe 6.0 使当今的数据中心受益(Benefits Data)
这并不是说PCIe 6.0已经对某人没有好处。在巨大的数据中心，我们都依赖于基于云的服务，每一点额外的带宽都是宝贵的。在这些计算机机架中，您会发现具有数十个或数百个CPU内核和高速SSD存储阵列的系统。PCIe带宽的改进将立即帮助减轻那些紧张的数据管道的压力。
拥有如此多的带宽意味着人工智能和机器学习应用程序可以在更短的时间内分析更多数据。这意味着在科学、工程和物理领域进行复杂工作的HPC（高性能计算）应用程序可以拓宽他们的视野。(High-Performance Computing)
即使是向数据中心发送大量数据以进行实时处理的IoT（物联网(Things)）(IoT)系统也将从额外的带宽中受益匪浅。(Internet)
PCI Express 6.0 之后会发生什么？
PCIe技术将存在很长时间，除非有人发明了一种更好的外围互连技术。英特尔(Intel)、AMD和Apple等公司正在利用其处理器封装内的芯片之间的相关技术做一些令人兴奋的事情。像AMD(CPUs)的Ryzen和Intel(AMD)的Alder Lake这样的(Alder Lake)CPU(Intel)都塞满了CPU内核(CPU)，它们需要移动大量数据。我们确信PCI-SIG可以从这些处理器内部发生的事情中学到一些东西。
What Is PCIe 6.0 and How Is It Different?
PCIe 4.0 motherboards are only now starting to ship to customers, but that’s not ѕlowing down the development оf thiѕ crucial periphеral connections standаrd. PCIe 6.0 is already on the table, with concrete improvements over the current cutting-edge standard.
Since PCIe is becoming fundamental in computers of all shapes and sizes, it’s worth talking about what PCIe is, what it’s used for, and what the new PCIe 6.0 will offer in the future.
The Basics of PCIe
PCIe is short for Peripheral Component Interconnect Express. Some of our readers who’ve been around computers for a while might remember the old PCI standard, but PCIe is to the original PCI standard as a fighter jet is to a paper airplane.
PCIe is both a protocol and a physical hardware connection standard. The most common PCIe hardware connection standard is the motherboard expansion slot. You connect expansion cards to these slots, and communication happens over the connecting pins. However, it’s possible to send PCIe protocol signals over other types of connections.
NVME SSDs using the M.2 connector can use PCIe, and this seems no different to the computer from an SSD connected through a standard PCIe slot. The Thunderbolt 3 and 4 standards also support sending PCIe signals over a cable. This is how eGPUs (external graphics cards) are possible.
PCIe devices send data in a serial fashion but across multiple, parallel lanes. An x16 PCIe slot on a computer’s motherboard can accommodate sixteen data channels at once. PCIe also offers x8, x4, and x1 slots. In general, graphics cards use the x16 slot because they need as much bandwidth as possible. While slower slots are usually physically shorter, it’s common for x16-length besides the primary one to be x8.
PCIe cards offer backward compatibility and cross-compatibility, so you can stick an x4 card in any PCIe slot that will physically accommodate it. It’s just that you’ll waste any PCIe lanes the x4 card doesn’t use. The same goes for using a PCIe 5.0 card in, for example, a 4.0 slot. It will work but be limited to the lowest common denominator.
Who Decides on the PCIe Standard?
The PCI Express standard is designed and approved by the PCI Special Interest Group (PCI-SIG), a consortium with members from the electronics and computer industry with a vested interest in the technology.
PCI-SIG was founded in 1992 as a group tasked with helping computer manufacturers correctly implement the Intel PCI standard. Today it’s a nonprofit organization with over 800 members.
The PCI-SIG board has AMD, ARM, Dell, IBM, Intel, Nvidia, Qualcomm, and more members. You might recognize these names as major computing device manufacturers, and having a shared standard makes their work much easier, not to mention the lives of their customers!
What Is PCIe Used For?
We’ve already mentioned expansion cards and SSDs above, so you’ve probably got a general idea of PCIe’s uses.
The PCIe standard connects just about any external peripheral device you can imagine. It offers a much wider bandwidth than USB, especially when looking at multiple lanes. PCIe also provides a direct path to the CPU, making it perfect for high-speed, low-latency applications.
Modern GPUs use sixteen lanes of PCIe bandwidth to maximize their performance, but not every peripheral needs that much bandwidth. The latest PCIe 4.0 SSDs use “only” four lanes, but that’s enough to blow the SATA standard clear out of the water. While SATA tops out at 600 MB/s, high-end PCIe 4.0 drives can move more than 7000 MB/s.
PCIe expansion cards also accommodate sound cards, video capture cards, 10Gb Ethernet adapter, WiFi 6 cards, Thunderbolt or USB controllers, and more. Peripherals that are integrated into your computer’s motherboard also use PCI Express. It’s just that the wiring is permanent and not in the form of a slot.
How Does PCIe 6.0 Improve on PCIe 5.0?
The headline improvement is usually a big leap in the data rate with every PCIe revision. That’s the amount of information that can be moved across the bus each second.
In that department, PCIe 6.0 does not disappoint. It fully doubles the already tremendous data transfer rate of PCIe 5.0 from 32 Gigatransfers per second (GT/s) to 64 GT/s per lane. Whereas PCIe 5.0 could shift 63 Gigabytes per second (GB/s), 6.0 can move up to 128 GB/s. That’s over an x16 connection, with more minor connections scaling down. It means an x8 PCIe 6.0 slot now has as much performance as an x16 5.0 slot.
This creates plenty of headroom for future GPUs and ultra-fast storage solutions. Not to mention incredible scope for external devices connected via PCIe or expansion cards that offer Thunderbolt and USB 4.
New Features in PCI Express 6.0
Making such a monumental performance leap in a single generation wasn’t easy. To achieve these numbers, the PCI-SIG engineers had to develop a few innovative new ways to move electrons around.
PAM4 Signaling
Quite possibly, the most significant change with PCIe 6.0 compared to previous generations of the interface is how data is encoded.
PCI Express 6.0 uses PAM4, which is short for Pulse Amplitude Modulation with four levels. If you know anything about electrical waveforms, you’ll know that the “amplitude” of the wave is how far the wave’s crest is from the baseline.
Older NRZ (Non-return-to-zero) PCIe encoding only had two amplitude levels per pulse during a clock cycle. PCIe 6 doubles that to four, increasing the amount of data encoded with each cycle.
Forward Error Correction (FEC)
While the PAM4 encoding method provides a significant boost to speeds, it also provides a big boost to bit errors. In other words, one arrives at its destination instead of a zero, and vice versa.
To combat this, PCIe 6.0 has a new Forward Error Correction feature, which checks to make sure data is getting where it should go without getting corrupted, with the help of a robust CRC (Cyclic Redundancy Check) implementation.
One danger of adding more error correction steps into the pipeline is that you’ll add more latency. Additional latency has been a growing concern with various high-speed computer components. Although they can shift more and more data, they take longer to react to a request for data, which can cause issues of its own.
FEC has been designed to target adding no more than two nanoseconds of latency compared to previous versions of PCIe, which is a tiny bit of extra latency no human can detect.
FLIT Mode
FLIT mode was another measure introduced to improve error correction in PCIe 6.0. It organizes data into units of uniform size using a dedicated onboard flow control unit. This is necessary to check packets for errors since you can apply an algorithm to each data packet and check if the packet still gives the result when it reaches the other end of the pipeline.
The thing is, it turns out that FLIT mode also brings significant efficiency gains in other places. It helps lower latency, makes bandwidth usage more efficient, and lets PCIe 6.0 do away with much of the encoding overhead from previous versions. So although PAM4 adds up to 2ns of latency, FLIT mode saves on latency in other areas.
L0p Mode
One interesting feature in PCIe 6.0 is L0p mode. This mode reduces the number of lanes a peripheral uses to send and receive data. So if your laptop is running on battery power and the GPU doesn’t need 16-lanes to do its current job, it will drop down to only using the number of lanes it needs, saving electricity by increasing power efficiency.
Should You Wait for PCIe 6.0?
If you’re thinking about buying or building a new computer soon, should you wait for PCIe 6.0 motherboards to come out first? It’s always tempting to try and build a futureproof computer. What if a new GPU or SSD comes out that needs PCIe 6.0 to reach its full potential?
The short answer to this question is that you don’t have to worry about waiting for PCIe 6.0. At the time of writing, PCIe 5.0 motherboards have only started rolling out to consumers, and even the most high-end current GPUs are nowhere near needing PCIe 5.0.
In benchmarks comparing flagship cards like the RTX 3080 or RTX 3090 running on PCIe 3.0 and 4.0, the difference in performance was somewhere between nothing and 3%. Yes, that’s right. We are only now reaching the limits of PCIe 3.0, and that’s only with the most expensive GPUs on the planet. Don’t sweat it—at least not for a few years.
Remember that PCI-SIG has only published their final PCIe specification for version 6.0 on paper. While the final specification won’t change, it will be some time before we see much hardware that supports it, at least in the consumer space.
PCIe 6.0 Benefits Data Centers Today
That’s not to say PCIe 6.0 isn’t beneficial to someone already. In the giant data centers, we all rely on cloud-based services, every extra bit of bandwidth is precious. Inside those racks of computers, you’ll find systems with dozens or hundreds of CPU cores and arrays of high-speed SSD storage. The improvements in PCIe bandwidth will immediately help take the pressure off those straining data pipes.
Having so much more bandwidth means that AI and machine learning applications could analyze more data in less time. It implies that HPC (High-Performance Computing) applications that do complex work in science, engineering, and physics can broaden their horizons.
Even IoT (Internet of Things) systems that send a flood of data to data centers to process in real-time will benefit massively from the additional bandwidth.
What Comes After PCI Express 6.0?
PCIe technology will be around for a long time unless someone invents a peripheral interconnect technology that’s radically better. Companies like Intel, AMD, and Apple are doing exciting things with the related technologies between chips inside their processor packages. With CPUs like AMD’s Ryzen and Intel’s Alder Lake stuffed to the gills with CPU cores, they need to move a tremendous amount of data. We’re sure the PCI-SIG can learn a few things from what’s happening inside these processors.
